1. Field of the Invention
The present invention generally relates to digital latch circuits and more specifically to a low-clock-energy latch circuit.
2. Description of the Related Art
Power dissipation is a significant problem in conventional integrated circuits. In many applications, the performance of integrated circuit devices is limited by the amount of energy consumed by the circuitry implementing a function rather than by the die area of the circuitry. A large fraction of the power dissipated in conventional digital integrated circuits is consumed in the clock network. The amount of energy that is consumed by flip-flops due to data transitions is small because the activity factor, the fraction of time the data input of the flip-flop toggles, is quite low, typically about 5-10%. In contrast, the clock input load and clock energy is a particularly important metric for determining the energy that is consumed by the latches and flip-flops. Hence reducing the clock-switched capacitance by a given amount produces 10-20× the power savings compared with reducing the data-switched capacitance by the same amount.
Conventional latches are often built as a pass-gate latch with tri-state feedback to produce a static circuit, as shown in FIG. 1A. Such a design requires a local clocked inverter (or two) to produce both polarities of the clock and has two clock loads on each of the pass gate and the feedback gate giving a total clock load of six or eight transistor devices.
FIG. 1B illustrates a conventional NOR latch 100 implemented with AND-OR-Invert (AOI) gates. The latch 100 is transparent when the clk (clock) input is high, so that the d input passes through to the q output. When the clk input is low the level of the d input is stored and q maintains the stored level of the d input at the q output. Each of the AND gates presents a clock load of two transistor gates, for a total clock load of four transistor devices.
FIG. 2A illustrates a latch circuit 200 corresponding to the conventional latch 100 shown in FIG. 1. The total clock load presented to Clk 220 is four transistor devices. The total number of transistors is sixteen, where each of inverters 222 and 224 include two transistors.
FIG. 2B illustrates a “push-pull” latch circuit 250 corresponding to conventional latch 100 shown in FIG. 1. The total clock load presented to an enable signal, E is four transistor devices. The total number of transistors is eleven, where each of the inverters includes two transistors. The PMOS transistors 256 and 258 are sized to be weak enough to allow D and dN to be written to S and sN when E is high, respectively. The weak devices are slow and do have a negative impact on the speed of the latch circuit 250. Specifically, the PMOS transistors 256 and 258 should be weak enough to be are overpowered by one of the two NMOS pull down stacks formed by NMOS transistor 260 and the NMOS transistor of inverter 262 or NMOS transistors 264 and 266. However, the PMOS transistors 256 and 258 are should be strong enough to pull up S or sN. These conflicting demands are difficult to balance, particularly as the fabrication process varies.
Accordingly, what is needed in the art is a latch circuit that reduces the clock energy by reducing the capacitance of clock loads. Additionally, the latch circuit should function independent of fabrication process variations.